Field of the Invention
The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory cells having a resistance switching element.
Description of the Related Technology
Resistive random access memory (RRAM) technology is a promising non-volatile memory technology candidate to potentially succeed flash memory technology, due to its simple structure and a potential for low-power operation. Recently, RRAM technologies having resistive memory cells arranged in “cross-bar” configurations have attracted considerable attention due to their potential for high bit-density integration. Memory arrays having cross-bar architectures, sometimes called “cross-bar arrays” or “cross-point arrays,” have a first plurality of conductive lines (e.g., bit lines) and a second plurality of conductive lines (e.g., wordlines) that cross the first conductive lines, and a plurality of memory cells formed at intersections of the first and second conductive lines. The memory cells include a resistive switching element that can switch between a high resistance state and a low resistance state in response to a current signal or a voltage signal. Despite the promising attributes, several technological challenges have been identified in implementing resistive memory devices having cross-bar architectures, including suppressing leakage currents through unselected/inhibited cells and delivering high drive currents through selected target cells during operation of the cross-bar arrays.
Leakage current paths formed through unselected memory cells during operation of the cross-bar arrays are referred to in the industry as “sneak current paths.” During operation of a cross-bar array, when addressing a selected target selected memory cell, parasitic current can flow through the sneak current paths formed through unselected memory cells that are in low resistance states. Such leakage currents can reduce the signal to noise ratio in reading the selected memory cell, which can in turn increase the rate of error in reading. The sneak path problem can be more pronounced in in passive arrays, especially situations where the low resistive state of the memory cell exhibits linear, or nearly linear current-voltage (IV) characteristics. Such linear or nearly linear I-V characteristics can result in a low signal-to-noise ratio, and can lead to a cell being misread due to the parasitic sneak current path via low resistance state neighbours.
To reduce the leakage currents through the unselected memory cells during operation, some cross-bar arrays employ selector devices. The selector devices can be two-terminal devices such as diodes, or three-terminal devices such as transistors. While selector devices can be effective in reducing leakage currents when included in the cross-bar arrays, some selector devices, especially three-terminal devices such as transistors, can take up greater lateral foot print compared to the resistance switching element, thereby limiting the physical bit-density of the memory array. Achieving a high bit-density in memory technologies is technologically and economically desirable for practical implementations of resistive memory technologies.
Various 2-terminal structures such as diodes (e.g. Schottky diodes, Zener diodes or tunnel diodes) or volatile switches (e.g. threshold switches, Mott switches, MIEC access devices) have been proposed as selectors for unipolar and bipolar RRAMs. Semiconducting materials and/or novel materials are used to build such diodes.
Two relatively important considerations in choosing a selector, in terms of the performance of a RRAM device, can be the drive current and the non-linearity factor. To be able to program and erase some resistive switching elements, selectors should be capable of delivering a high drive current. For example, to switch a resistive switching element having a lateral dimension of 10 nm×10 nm with a current of 1 uA switching current, a selector needs to supply at least 1 MA/cm2. In addition, the non-linearity factor (or rectification factor or on/off ratio), which can be defined as a ratio between the current thorough the selector at a switching voltage and the current through the selector at half the switching voltage, should be at least 1000, for example, to enable relatively large memory arrays, e.g., memory arrays exceeding 1 Mbit in size. Available two terminal selector options fall short of desirable performances with respect to one or both of the drive current and the non-linearity factor considerations. Other selector options employ materials that are very difficult to integrate using conventional CMOS process technologies, such as platinum. Therefore, there is a need for a two-terminal selector device that can deliver both high drive current and high non-linearity factor, which can also be fabricated using CMOS-compatible process technologies.